Simulated PDP-15 panel

Parent Category: Projects Category: BlinkenBone panel simulations Written by Administrator

panel pdp15 small

(Click to enlarge)


The PDP-15 is the last of DEC's 18-bit architectures, which began with the PDP-1.

See here the installation of the Institute for Numerical Mathematics in Goettingen, 1972 :

pdp15 numeric goettingen


Lately I was donated a physical PDP-15 panel, formely used in the "DFVLR" Göttingen, now DLR. (Finally all this "BlinkenStuff" pays off!) And after making another physical BlinkenBone box out of it (yawn!), also the Java simulation was a must-have (pain!).

blinkenbone pdp15+panelsim small

One for you, one for me!

Download and run

You can download a distribution with Java panel, SimH, a demo application and instructions here at GitHub. One startup script is "pdp15_focal", a more compelx installation is  "pdp15_xvmdosrsx".

Operating the Java panel

As usual the panel simulation is a platform-independent Java application.

If you never worked with DEC console panels before, check out the tutorial for the PDP-11/40 first.
The PDP-15 is a bit easier to operate, since it has separate ADDRESS and DATA switches, so you do not need to save an address with LOAD ADR. And for EXAM and DEPOSIT there are separate THIS and NEXT switches for optional address autoincrement.

All switches are operated by clicking with the mouse onto them. More fun is finger-tapping on a large touch screen monitor. You can switch several keys at once by holding the mouse button down and dragging over them.

The two rotary knobs to the right are special:

  • on first click they change from normal "side view" to "top view", so you can see better the printed marks.
  • in "top view" a click to the left half of a knob rotates it counter-clock wise, a click in the right half rotates clock-wise.
  • After a few seconds idle time the display changes back to "normal".
panel pdp15 knobs normal

panel pdp15 knobs frontal

Differences to the real thing

Due to limitation of SimH (and due to my own ones!) there are some differences to a real PDP-15.

  • SimH does emulate on architecture level, but does not reproduce the actual electronics. So some hardware related functions are not available.
  • And I've never see a running PDP-15 (are there any?), so all functions are concluded from paper documentation.

Most switches perform a function (or will in the future ...)

  • EXEC does nothing. It should execute the opcode set by the DATA switches.
  • CLOCK and BANK MODE simply turn on the corresponding lamps.
  • PROT is not yet implemented.
  • The single step switches SING TIME and SING STEP perform like SING INST.

The PDP-15 executes an instruction in several MAJOR STATE phases, each divided in TIME cycles. SimH does emulate the PDP-15 on register level, so "CYCLE" and "TIME" stepping cannot be performed.  Likewise, the "MAJOR STATES" and "TIME STATES"  indicators are just a fake.

Most lamp indicators also work as expected. A software low pass make them "lazy", and dim lamps are painted in a browner color.
You find more about the lamps at bottom of the PDP-8/I page.

Bit numbering

Every number in the PDP-15 world is written octal. There are 18 data bits and 15 address bits.

As usual on earlier DEC machines, bit strings are written with the high-most bit to the left ... as today.
But the bit numbers are reversed: The most significant bit MSB (which has the highest value in integer representations) has number "0",
then bit numbers increase from left to right.

panel pdp15 bit number

Bit numbers are reversed

First let's look onto 18 bit DATA.
Modern bit numbers are:  17, 16, 15, ... 0.
This appears on the PDP-15 panel as: 0, 1, 2, ... 17.

Got it? Then lets make things more complicated.
15-bit ADDRESSes are shorter than 18-bit DATA words, and the least significant bit (DEC bit number #17) of addresses and data must kept aligned.
Only solution is: number the address bits from 3 upto 17.
Modern address bit numbers are: 15, 14, 13, ... 0.
PDP-15 address bit numbers:  3, 4 ,5 ... 17 !

No wonder this notation didn't survive.

DEC's panel reference

Here comes the DEC documentation for the switches. The documents are "PDP-15 Systems Reference Manual" (Aug 1969, DEC-15-BRZA-D), Chapter 10 "Console", and "XVM system reference manual (Jun 1976, EK-15XVM-OP-001).pdf", chapter 4.

"The PDP-15 console (see Figure 10-1) provides access to, or control over, virtually every portion of the PDP-15. All registers, buses, and controls are multiplexed down a single console cable to display the equivalence of 24 registers and 34 control functions. The console provides extensive control for real-time debugging and comprehensive man-machine interaction during checkout.

The following momentary contact switches are on the console panel: Start, Execute, Continue, Stop, Reset, Read In, Deposit This, Deposit Next, Examine This, Examine Next.

Switch Function
DATA These 18 switches may be read indirectly into the accumulator by the execution of a OAS (OR accumulator content with switches content) instruction in an operating program. Data may be inserted manually into the machine with these switches by means of the DEPOSIT and DEPOSIT NEXT keys.
ADDRESS The memory address required by the START, READ IN, EXAMINE, and DEPOSIT keys is supplied by these switches. When one of these keys is depressed, the address given by the address switches is loaded into the MA (memory address) register and the key instruction is executed.
REG GROUP Selects which of two groups of 12 registers to be selected by the register select switch. In the OFF position the normal registers may be viewed while the ON position allows viewing of the maintenance registers. (See Register Select Switch).
CLOCK The ON position disables the real-time clock from issuing program interupt (PI) requests.

With this switch in the ON position, the processor will repeat the key function depressed by the operator at the rate specified by the repeat clock.

Start - program execution will restart at the repeat speed after the machine halts.

Execute - the instruction in the data switches will be executed at the repeat
        clock rate.

Continue - program execution will continue at the repeat speed after halting.

Deposit: This, Next. Examine: This, Next - the Deposit, Deposit Next or Examine
        Next function will be repeated.

Depressing STOP or turning off the repeat switch will halt the repeat action.

BANK MODE When set (back half of switch pressed), pressing START causes the system to start in Bank mode permitting direct addressing of 8,192 (17777o) word of core memory. When switch is not set (front half pressed), pressing START causes the system to start in Page mode permitting direct addressing of 4,096 (7777o) words of core memory.
SING TIME Halts execution of the program after each time state has been completed.
SING STEP Halts execution of the program after each major state has been completed.
SING INST Halts program execution after each instruction has been completed.
START Initiates program execution at the location specified by the address switches.
EXEC Executes the instruction in the data switches and halts after execution.
CONT Resumes program execution from the location specified by the program counter
(PC). Also used to advance machine while in single time, step or instruction.

Halts the processor after the completion of the present instruction.

STOP is the only switch active while the machine is running. If, at any time, the machine must be reset while the RUN light is on, the RESET and STOP switches should be pressed simultaneously. This is an unconditional reset procedure that should be used with caution, beacuse data can be lost.

RESET Generates a power clear signal which clears all active registers and all control
flip-flops except the program counter (PC).
READ IN Initiates the read-in of paper tape punched in binary code (each set of three 6-bit lines read from tape forms one 18-bit computer word). Storage of words read-in begins at the memory location specified by the ADDRESS switches. At the completion of tape read-in, the processor reads the last word entered and executes it.
DEPOSIT THIS Deposits the contents of the data switches into the memory location specified by the address switches. After the transfer, the memory locations address is in the OA (operand address) register and the contents of the accumulator switches are in the MO (memory out) register.
DEPOSIT NEXT Deposits the contents of the data switches into the location given by OA ±1. This permits the loading of sequential memory locations without the need of loading the address each time.
EXAMINE THIS Places the contents of the memory location specified by the address switches into the memory buffer register. The address is loaded into the OA (operand address) register.
EXAMINE NEXT Places the contents of the memory location specified by the OA + 1 (operand address plus 1) into the memory buffer register. Sequential memory locations may be examined using the Examine-Next switch.
PROT Initiates the memory protect feature. When utilized, the protect feature prevents the read-in of data into the specified "protected" memory locations.
Register Select The 12 position Register Select rotary switch can select the following registers for viewing in the REGISTER indicators (under control of the Register Group switch).

Register Group Switch OFF:

    AC      Accumulator
    PC      Program Counter
    OA      Operand Address
    MQ      Multiplexer Quotient
    L, SC   Priority Level/Step Counter
    XR      Index Register
    LR      Limit Register
    EAE     EAE
    DSR     Data Storage Register
    IOB     I/O Bus
    STA     I/O Status
    MO      Memory Out

Register Group Switch ON:

    A BU    A Bus
    B BU    B Bus
    C BU    C Bus
    SFT     Shift Bus
    IOA     I/O Address
    SUM     Sum Bus
    MI      Maintenance I
    M2      Maintenance II
    MDL     Memory Data Lines
    MA      Memory Address
    MB      Memory Buffer
    MST     Memory Status

Power/Repeat Switch A variable-pot/switch provides the POWER ON/ OFF control at one end of its rotation and variable repeat speed (approximately 1 Hz to 10 kHz) over the remainder of its rotation.


Indicator Function
POWER Indicates that the power supply voltages are at operating levels.
RUN Indicates that program execution is in progress.
CLOCK Indicates that the real-time clock facility is enabled.
DCH ACTIVE Lights when the data channel is beeing serviced, i.e., data is being transferred
between core memory and a device via the I/O bus.
API ENABLE Lights when the automatic priority interrupt system is activated.
API STATES ACTIVE Indicates  API level(s) active.
0-3: Hardware levels.
4-7: Software levels.
MAJOR STATES FETCH: Indicates that the processor is in the Fetch state.
INC: Indicates that the processor is in the Increment state.
DEFER: Indicates that the processor is in the Defer state.
EAE: Indicates that the processor is in the EAE (extended arithmetic element) instruction state.
EXEC: Indicates that the processor is in the Execute state.
TIME STATES 1,2,3 Indicates the processor time states. When all time states are off, machine is in
time state 2A of the Add instruction.
PI ACTIVE Indicates that a program interrupt is pending service.
PI ENABLE Indicates that the program interrupt system is enabled (under program control).
MODE INDEX Indicates that the processor is operating in Page mode and therefore indexing
can be accomplished.
LINK Display state of Link bit.
INSTRUCTION Displays contents of 6-bit program word instruction field.
0-3: Displays the instruction operation code.
DEFER: Indicates that the operand is indirectly addressed.
INDEX: Indicates that the operand address is indexed when in Page mode or that the upper 4K (of an 8K bank) is addressed when in Bank mode.
MEMORY BUFFER 00-17 Displays the content of the currently addressed memory address.
REGISTER 00-17 Used with the setting of the REG GROUP and Register Select switches to display:
a. Data in a register
b. Data on a bus
c. Coontrol signal levels




Some additional notes

Switch orientation: The switches are "butterfly" switches, which can be pressed down facing to you or facing to the panel.
If a switch faces the panel a white "I" is visible, indicating the switch is in the "active" state (on ADDRESS and DATA interpreted a "1" bit value).

POWER: the PDP-15 is powered by rotating the upper knob "REPEAT RATE" (labeled "FAST").
The logic is like an old radio volume control.
So when modifying the repeat rate, be sure not to switch the machine of by accident!

Booting from paper tape: READ IN reads a paper tape strip and starts execution.
Under SimH the file with the paper tape image is specified like

sim> set realcons bootimage=focal15.bin

REPEAT logic: This is something very cool! Several "momentary action" switches can be fired automatically with varying frequency, if you keep them pressed down.

panel pdp15 repeat

Stuff related to the "REPEAT" feature

The REPEAT feature is enabled with the "REPT" switch.
The frequency is set with the upper knob. Originally you could select up to 10 kHz, but the simulations limits this to 100 Hz. ('cause every command is echoed on SimH's console).
These buttons have auto repeat: START, EXEC, CONT, EXAM THIS/NEXT, DEPOSIT THIS/NEXT

So you can single step in high speed by setting REPT and SING INST, then hold CONT down.

Or you can initialize a whole memory area by repeated DEPOSIT NEXT.

Register display logic

24 different machine registers can be displayed on the REGISTER lamps, by operating the REGISTER SELECT knob and the REG GROUP switch.

panel pdp15 register select

Stuff related to "REGISTER SELECT"

IF REG GROUP is not active the registers whose names are printed on the left knob half are displayed.
And if active, the register printed on the right half is selected.
In the example image above: PC on left half, visible if REG GROUP inactive; and BBU on right half.

Many registers are for diagnostics of the electronic and will never be simulated by SimH.
Others may be implemented as my knowledge about the PDP-15 increases.
At the moment these registers are implemented:

  REG GROUP inactive:
AC accumulator
PC program counter
OA Operand Address (address of exam/deposit, or effective address of last memory referencing operand when executing instructions)
MQ Multiplier Quotient
L, SC Priority Level / Step Counter
XR Index Register
LR Limit Register
MO Memory Out  (same as MEMORY BUFFER)
  REG GROUP active
MDL Memory Data Lines (same as MEMORY BUFFER)
MMA Memory Address, last used
MMB Memory Buffer (same as MEMORY BUFFER)