Simulated PDP-11/20 panel

Parent Category: Projects Category: BlinkenBone panel simulations Written by Administrator

A journey of a thousand miles begins with a single step

  blinkenbone pdp1120 panelsimClick for large version

The virtual PDP-11/20 console panel

I was lucky to borrow a 11/20 from the Computer Museum of GWDG in Göttingen, Germany.
Of course I made immediately another BlinkenBone Java front panel simulation of it:


Real PDP-11/20 below, touch-screen monitor with BlinkenBone simulation sitting above

About the PDP-11/20

The 11/20 is the first PDP-11 build and sold. It was introduced 1970.
On first look - with its DECtape and Papertape periphery - it appears like the follow-on to some PDP-8.

Some unique construction features were dropped in later PDP-11's:

  • Lightbulbs in the panel (all later PDP-11s had LEDs)
  • Front panel circuit board plugged into the backplane (later the panel was mounted separate from the backplane)
  • Switches are those of the PDP-8/e
  • CPU is build with hardwired logic (other PDP-11 processors were implemented in micro code, much later then as FPGAs.)

All this makes the 11/20 look like a sucessful prototype. You wouldn't have expected the historic impact of this machine!

pdp11 20 brochure pdp1120 manual cover



Since all blinkenlight -PDP-11s have very similar panels, see the PDP-11/40 for a thorough explanation.


The ADDRESS and DATA lamps are as on all DEC panels.

The PDP-11/20 is a 16-bit machine. The ADDRESS lamps 17 and 16 have no function, but are always ON, if an address in the IOpage is set.
So addresses 177777..160000 are displayed as 777777..760000.

The PDP-1/20 has no virtual memory: There is no MMU nor I/D data space nor KERNEL/SUPER/USER mode.
Still there are some indicators on the right half, these help track internal processing in "single cycle" mode. This is only needed when debugging errors in the circuitry.

The 11/20 CPU is not implemented with a micro-machine, but with hardwired logic.
So instead of micro-program flow, an opcode is executed in fixed phases, each characerized by diverse "cycle" signals. These are displayed with the lamps:

  • FETCH: load opcode from memory
  • EXECUTE: run data from registers through the ALU and write back.
  • SOURCE/DESTINATION, ADDRESS: additional memory cycles to access operands from memory and index data.

SimH does not simulate any of this, so a fixed pattern of "glowing" lamps is shown on RUN. And the "Single-CYCLE" step mode is not implemented.


The panel switches have the same shape as those on the PDP-8/e.

The S-INST/S-CYCLE switch is has no function: SimH can't single-step the hardwired execution logic. Every CONT in HALT mode performs a single instruction step.

The keylock switch is rotated counter-clockwise by clicking somewhere left of the switch center, and rotated clock-wise by click right of the center.
"LOCK" disables all keys. And setting the switch to "OFF" terminates SimH (almost).

If the PDP-11/20 is a true 16 bit machine, then why has it 18 address switches?
Answer: Forsight (but not enough)! Bits 17 and 16 are "reserved" for later memory expansion. It was planned to expand the 64K address space to 256 KBytes. But the PDP-11 lived much much longer than expected. UNIBUS address space was limited to 18 address bits, but with a local memory bus 22 bits could be addressed. In 1978 the VAX introduced a much greater architecture, the PDP-11 was not further enhanced and starved to death on memory for the next 20 years.

Running a light

DEC documentation does not specify, what in in RUNning state is to be displayed on the DATA lamps, I've been creative here.

But definitely after a HALT opcode register R0 is displayed on DATA.
So the "Running light" program is this:

        1                                    .title    PDP-11/20 running light       
2                                    ; This program shifts endlessly a bit in R0
       3                                    ; and shows each value on the DATA LEDs, then HALTs.
       5                                    .asect
       6 001000                             .=1000        ; program loads at 1000
      8                                start:
      9 001000 005000                      clr    r0    ; set bit 0 in R0
      10 001002 005200                      inc    r0    ;
      11                                loop:
      12 001004 006100                      rol    r0
      13 001006 000000                      halt        ; use CONT switch to proceed
      14 001010 000775                      br    loop

Toggle this code in with LOAD ADDR and multiple DEP's.
Start with "LOAD ADDR" and START.
You have to press "CONT" after each iteration.

The distribution provided on GitHub is booting and running a more interesting software: the "1970 Papertape BASIC". See next page!