EDDA 3 - Processor Architecture

Parent Category: Articles Category: EDDA 3 - An Early Transistorized Process Computer Written by Administrator

EDDA 3 implements a Havard architecture with memory-mapped I/O. Program memory ("Programm-Matrix") and data address space are logically totally isolated from each other. Via the data address space the following can be accessed: some numerical constants, core memory, registers with special functions (which are actually part of the CPU), and registers for interfacing peripheral equipment.

In the architecture schematic, you see that processor control ("Programsteuerwerk") and processor data path ("Rechenwerk") are well separated. Program memory is considered as being part of the processor control unit. There is no clear distinction between core memory, i/o registers and processor data path.

architektur schema

(Translation: "Programsteuerwerk" = program control unit = processor control, "Befehls-Nr" = instruction number, "Rechenoperation" = calculation command, "Festwertgeber" = constant value producer, "Kernspeicher" = core memory, "Rechenwerk" = calculation unit = processor data path, "Waage" = scale, "Tastatur" = key board, "Eingabekanäle" = input channels, "Ausgabekanäle" = output channels, "Ziffernanzeige" = digit display)

EDDA 3 does not operate on binary but on decimal basis! It works with integer arithmetic.

Word length of the data memory is 4 decimals, thus values from 0 to 9999 can be represented.

Word length of the program memory ("Programm-Matrix"): 30 soldering positions for diodes. So EDDA 3 can be called a "30 bit" computer.

Address length for program code and data: 2 decimals. Therefore, programs with 100 instructions can run directly and the memory cells 0 to 99 can be accessed directly. That’s why the program counter ("Befehls-Nr.") only has two decimals.

Size of the program memory ("Programm-Matrix") on basic setup: 100 instructions. There’s an additional switch over for address spaces, implemented by a segment register, thus a maximum of 10 banks with 100 instructions each can be processed.

Size of the data memory on basic setup is 100 addresses, including 30 core memory cells, 6 special registers (shift registers, instruction number, index address), and the rest for peripherals.

Further core memory modules can be added, however, they can only be addressed indirectly via the index register 99.

As in so many other computer architectures the basic address space (here: addresses 00 to 99) isn’t sufficient to address all possible extensions for memory and peripherals. Therefore, extra modules for EDDA 3 are also addressed either indirectly (over registers 64/99) or by segment registers (over registers 51/59).

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CPU and Instruction Set

The processor consists of program counter ("Befehls-Nr."), instruction decryption, buffers, clocking, and arithmetic unit, spreaded over 20 expansion cards. Internally it works number-serially, meaning that the four decimal digits of the data words are added or subtracted digit-wise in sequence. The adder for two single-digit decimal numbers is implemented by a diode matrix, tabulating the results of possible additions.

All instructions are directly processed in the memory ("memory-memory architecture"). Except for the program counter, there are no CPU registers.

The EDDA 3 CPU processes only three (!) types of instructions, these being in fact only variants of each other. There are:

  1. "ADD": Memory address X + memory address Y => memory address Z
  2. "SUBTRACT": Memory address X - memory address Y => memory address Z
  3. "SUBTRACT FROM CONSTANT":  Constant X - memory address Y => memory address Z
    (Here the minus sign is written as "(-)" instead of "-".)

If the result of an addition or subtraction produces an overflow or a negative result, the next instruction is executed, else the next instruction is skipped ("Skip on Non-Negative"). Skipping is disabled if the special jump flag "PS" in the instruction is cleared. The skipped instruction is typical a write to the program counter, written with instruction format 3 as "Constant destination address (-) 0 => memory address 50".

So each instruction is either an addition or a subtraction, and depending on the calculation result the next instruction is executed or skipped. Many other CPU opcode you would expect are just special cases of these generic opcodes.

  • Data can be moved from one memory location to another unchanged when one operand is the constant "0" on address 0 (see below "Data Address Space").
  • Because the program counter also was placed in the address space, unconditional jumps could be made by directly writing to the program counter at address 50.
  • Testing a memory location for a given value is done by subtracting the memory value from the test value, writing the result to the dummy register, and skipping on the negative condition.
  • Calculated jumps can be made by writing a core memory value to the program counter.
  • If the result of the calculation is not needed (e.g. during tests), it can be written to the dummy register no. 69.

Numerical constants can be directly given in instruction #3, they can be 00 to 99. In instruction #1 and #2, addresses 0, 1 and 2 access the 4-digit constants 0, 1, and 1000.

A Single Instruction Set Computer

Because of its minimalistic instruction set, EDDA 3 is also of interest for the theoretical computer science. It implements the almost smallest possible instruction set being Turing-complete. Essentially EDDA 3 can emulate any other computer (if arbitrary amount of RAM could be added)!

This is because EDDA 3 executes the "Subtract and branch if negative" instruction, see the Wikipedia article about extreme RISC architectures "One instruction set computer (OISC)". There the OISC is also described as URISC (Ultimate Reduced Instruction Set Computer) but is treated as pure theoretical concept.

EDDA 3 comes very close to a real and existing OISC.

 

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