There's no way to repair a PDP-11 without logic analyzer. Today you have typically two choices:
- buy an used ancient LA from the good old days. On the plus side, these are cheap and can have 100+ probe channels. Drawbacks are: big case, bad integration into the modern workplace (typically file transfer over floppy disk!), reliability, lack of trace memory and lack of bandwidth.
- get a modern USB and FPGA based device. These integrate well, bandwidth is typically 500Msamples/sec, many options for trace memory exists. However low price devices scale not behind the invisible wall of 34 probe channels.
So when working with logic analyzers on PDP-11s, the main challenge is to deal with limited probe count. In theory QBUS traffic needs 42 signals wires on its own, before any tracing in the circuitry can start. But you can get a feeling of bus traffic by just watching lower 16 DAL lines and some protocol signals.
Additionally to 42 QBUs signals, QProbe can also latch DAL on SYNC and route 22 stabilized adddress lines to the LA too. Then you'd need 42+22 = 64 LA lines for QBUS traffic.
To help a bit, QProbe allows to connects flexible only a subset of QBUS cables to the LA, leaving other LA signals for circuit diagnostics.
Seven 8-channel plugs for LA cables are provided, labeled "A", "B", etc. until "F".
QProbe supports the "Zeroplus" probe standard: A probe cable carries 8 signals on a standard flatcable. Typical 2x8 pinheaders are crimped to the cable.
Output on the LA is (view onto the LA case):
|Male signal pins
|upper row: Signals
|lower row: Ground
QProbe contains male sockets. View onto the connector front:
|Male signal sockets
|upper row: Signals
|lower row: Ground
Mapping LA channels to QBUS signals
Depending on the CPLD operation mode, SYNC-demultiplexed ADDR signals can be routed to the LA in addition to the ADDR/DATA muxed DAL lines.
There is support for 3 signal mapping styles:
"Hard wired mapping": QBUS DAL<15:00> are always connected to probes "A" and "B". BS7 goes always to "C.6", SYNC goes to "C.7".
I can imagination no situation were you don't need to see these.
"Fixed position jumper mapping": To display the regular QBUS data cycle, WTBT, DIN,DOUT, RPLY, REF are needed. As I have a 70 channel LA and want to see these always, jumper brigdes are provided to save on plug wires. Also demuxed ADDR can be routed to the LA ports too: ADDR<15:8> to "D", ADDR<7:0> to "E. On Port "C" Either ADDR<21:16> or DAL<21:16> can be seen.
"Patch panel mapping":For all other signals a patchpanel is provided. Every remaining QBUS signal can be routed freely to any LA probe plug. This allows for greatest flexibility and ensures no LA channels are wasted.
Organizing all these wires
From painful experience, QProbe has functions to tame the LA cable tree.
- it can serve as cable hub, to route all LA probes into one place, then going from that into the PDP-11.
- it allows for longer LA cables, as mechanical dimensions in a PDP-11 may be challenging.
Long flatcables introduce additional impedance, causing signals to reflect between the high-impedance LA inputs and the QBUS signal sources.
The reflections oscillate between QBUS and LA and cause additional signal spikes.
They can be damped by adding in-series resistors.
Synthetic CPLD-to-LA signal
As noted above "ADDR<21.00>" signals are generated by CPLD and normally contain the SYNC-demultiplexed address from DAL<21:0>
However, own CPLD logic may use these ADDR signals to expose other information, for example to trigger a logic analyzer at certain complex bus conditions.
In this case some of ADDR<21:0> loose their meaning as "Demultiplexed address".
Already implemented is a HALT catcher:
When running diagnostic programs on a PDP-11, you typically execute a HALT opcode on some error condition. You like to trigger the analyzer on that HALT event, but there is no bus line indicating a CPU HALT (QBUS HALT is input to the CPU only). In fact a QBUS-CPU never HALTs like a UNIBUS CPU, instead the microcoded ODT monitor starts and polls the console UART for input at high frequency.
This is used to recognize a HALT condition: A special CPLD mode sets the ADDR<0> pin when two consecutive accesses to UART address range at 777560..777566 are detected. Regular code which polls UART in a tight loop needs at least to fetch a program opcode between two UART accesses, only micro coded ODT can access UART without generating other bus cycles.
There's one exception: If the CPU executes program from a memory cache, no program fetches are visible on QBUS and the CPLD logic gives false HALT.
Sample QBUS cycle measurement
Here comes an example logic analyzer screen shot ... from heavy QBone debugging. Many signals are not QBUS related, and only DAL, BS7, DIN, DOUT and RPLY are really important.
All signals levels are inverted (a logic 1 is a 0 volt level), except DAL ... we want to see the address/data values.
- at cursor "A" the CPU latches address in DAL onto the bus, address value is hex 0x1798 = octal 13630.
- Then the CPU asserts DIN to issue a READ cycle.
- A memory responds to the address, fetches the data and asserts them to the CPU at cursor "B" with RPLY. The data value is hex 0xfffa = octal 177772
- The CPU reads data from DAL and acknowledges by negating DIN, the memory card removes data from DAL and negates RPLY.
Importance of inline-terminators
High frequency signals behave like water waves: they get reflected on cable ends, if the receivers impedance does not match cables wave resistance. Logic analyzer inputs have an impedance of > 100kOhm, but if the probes are lengthed with flat cable we get 100-150 ohm per meter extra. This additional impedance must be damped by resistors inserted into the wires. QProbe has positions for these resistors.
This is indeed important, see UniProbe example. Here the transition of UNIBUS address line ADDR00 from "inactive" to "asserted" (logic 0 to 1) is shown.
The "blue" signal is measured at the UNIBUS pin, "red" is at the logic analyzer inputs via 50cm flat cable. The scope had a bandwidth of 200MHz, scale division is 20ns.
Without inline terminators, you see:
- delay by the flat cable is about 7 nano seconds.
- Without inline resistors, there are heavy signal reflections.
- At the LA input, the reflections reach the logic threshold voltage of 1.5 V.
- the reflections even impact UNIBUS signal quality.
The frequency of the oscillation is surprisingly low: 40ns peak-to-peak, about 25MHz. Apparently the cables form an inductivity-capacity (LC) resonator .
Here with 82 ohm terminators the reflections are damped, while preserving signal levels and timing:
The best resistors values depend from quite a few factors and must be optimized individually for each probe&logic analyzer combination.