PDP11GUI Memory Management window

Parent Category: Tools Category: PDP11GUI Written by Administrator

In the PDP-11 world, there are two addressing schemes: “physical” and “virtual.” Most PDP-11 (11/70 and newer) overcome the limitation of a 16 bit address space by providing 22 physical address lines, so they can address 4 MB of memory. Since all CPU registers remain 16 bit wide, programs can still address only 64 kBytes. So a memory managment unit (MMU) maps this “virtual” 64kB space of running programs to 22 bit physical address space. This way many programs and the operating system and device handlers can run parallel, each addressing 64 kB of data and 64 kByte of program code.

Most PDP11GUI operations are performed on 18 bit or 22 bit physical addresss. However, program counter content is always 16 bit virtual, so for program execution, MACRO-11 program loading and disassembly, PDP11GUI must convert 22 bit addresses to 16 bit addresses and vice versa.

To be able to do this, a simulation of the PDP-11 MMU is built into PDP11GUI. The PDP11 MMU consists of a global memory relocation table (3 * 32 “PAR”/ “PDR” registers) as well as 4 MMU status and control registers. For a thorough understanding, see the “pdp11 processor handbook”, Chapter 6, pdf pages 151ff.



The MMU window shows the state of the internal MMU and the resulting effective memory map. It is read only.

To change the MMU registers directly, use the MMU register window. You must have a valid MMU device definition in your machine description file.

The “Refresh” button reads the MMU register values from the target PDP-11 into the simulated MMU and calculates a new memory map. The resulting memory map depends on

  • the MMU page registers (PAR/PDR). These will not change very often (the operating system will change them, if it creates or destroys processes, or pages memory in and out to disk)
  • the MMU status and control registers, Most important is the “enable relocation” bit 0 in SR0, which enables or disables the whole MMU.
  • the current CPU mode. (CPU PSW register). This will change often depending on what your operating system is doing. If you are just playing with your PDP-11 in console mode, it will always be “Kernel”.
  • whether the address is used for code fetch (“Instruction space”) or data adressing (“Data space”). In fact there are two independent memory maps for I and D space.

MMU is quite an experimental feature and has not yet been tested for other then 1:1 memory maps. More to come!