UniProbe - an UNIBUS signal adapter

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Category: UniProbe - an UNIBUS signal adapter

All 56 Unibus signals are routed to plugs for logic analyzer ("LA") probes.

There's no way to repair a PDP-11 without logic analyzer. Today you have typically two choices:

• buy an used ancient LA from the good old days. On the plus side, these are cheap and can have 100+ probe channels. Drawbacks are: big case, bad integration into the modern workplace (typically file transfer over floppy disk!), reliability, lack of trace memory and lack of bandwidth.
• get a modern USB and FPGA based device. These integrate well, bandwidth is typically 500Msamples/sec, many options for trace memory exists. However low price devices scale not behind the invisible wall of 34 probe channels.

So when working with logic analyzers on PDP-11s, the main challenge is to deal with limited probe count. In theory UNIBUS traffic needs 56 signals wires on its own, before any tracing in the circuitry can start. But you can get a feeling of bus traffic by just watching data, a few lower address lines and some protocol signals.

To help a bit, UniProbe allows to connects flexible only a subset of UniBus cables to the LA, leaving other LA signals for circuit diagnostics.

 

 

Probe connectors

Seven 8-channel plugs for LA cables are provided, labeled "A-Lo", "A-Hi", "B-Lo", etc. until "D-Lo".

UniProbe supports the "Zeroplus" probe standard: A probe cable carries 8 signals on a standard flatcable. Typical 2x8 pinheaders are crimped to the cable.

Output on the LA is (view onto the LA case):

Male signal pins								Usage
7	6	5	4	3	2	1	0	upper row: Signals
G	G	G	G	G	G	G	G	lower row: Ground

UniProbe contains the mating female sockets. View onto the connector front:

Female signal sockets								Usage
0	1	2	3	4	5	6	7	upper row: Signals
G	G	G	G	G	G	G	G	lower row: Ground

 

Mapping channels to UNIBUS signals

There is support for 3 signal mapping styles:

"Hard wired mapping": UNIBUS DATA <15:00> and ADDR<07:00> are always connected to probes "A-Lo", "A-Hi" and "B-Lo".
I can imagination no situation were you don't need to see these.

"Fixed position jumper mapping": To display the regular UNIBUS data cycle, signals ADDR<17:08>,C0,C1,MSYN,SSYN are needed. As I have a 70 channel LA and want to see these always, jumper brigdes are provided to save on plug wires.

"Patch panel mapping":For all other signals a patchpanel is provided. Every remaining UNIBUS signal can be routed freely to any LA probe plug. This allows for greatest flexibility and ensures no LA channels are wasted.

 

Additionally, a special "IOPAGE" signal is added, which decodes addresses in the 760000 range. Its just the OR of ADDR<17:13>, so five wires are replaced by a single wire for "IOPAGE". Only if ADDR<17:13> are all Low (= logic "1"), IOPAGE is also Low (= logic "1"). Together with A<07:00> this allows to follow peripheral accesses and program execution with just 9 address lines.

Organizing all these wires

From painful experience, UniProbe has functions to tame the LA cable tree.

• it can serve as cable hub, to route all LA probes into one place, then going from that into the PDP-11.
• it has mounting holes to allow for struts and a lid to keep all the bread board cables flat on surface.
• it allows for longer LA cables, as mechanical dimensions in a PDP-11 may be challenging. 
  Long flatcables introduce additional impedance, causing signals to reflect between the high-impedance LA inputs and the UNIBUS signal sources.
  The reflections oscillate between UNIBUS and LA and cause additional signal spikes.
  They can be damped by adding in-series resistors.

 

Importance of inline-terminators

High frequency signals behave like water waves: they get reflected on cable ends, if the receivers impedance does not match cables wave resistance. Logic analyzer inputs have an impedance of > 100kOhm, but if the probes are lengthed with flat cable we get 100-150 ohm per meter extra. This additional impedance must be damped by resistors inserted into the wires. UniProbe has positions for these resistors.

This is indeed important, see example. Here the transition of address line ADDR00 from "inactive" to "asserted" (logic 0 to 1) is shown.

The "blue" signal is measured at the UNIBUS pin, "red" is at the logic analyzer inputs via 50cm flat cable. The scope had a bandwidth of 200MHz, scale division is 20ns.

Without inline terminators, you see:

• delay by the flat cable is about 7 nano seconds.
• Without inline resistors, there are heavy signal reflections.
• At the LA input, the reflections reach the logic threshold voltage of 1.5 V.
• the reflections even impact UNIBUS signal quality.

The frequency of the oscillation is surprisingly low: 40ns peak-to-peak, about 25MHz. Apparently the cables form an inductivity-capacity (LC) resonator .

Here with 82 ohm terminators the reflections are damped, while preserving signal levels and timing:

The best resistors values depend from quite a few factors and must be optimized individually for each probe&logic analyzer combination.

Details

Written by: Administrator

Parent Category: Tools

Category: UniProbe - an UNIBUS signal adapter

When build for Standard UNIBUS, UniProbe is plugged into the backplane "end" sockets and must act as bus terminator. It is identical to a regular M9302 terminator card then.

 With inline resistor packs we can build it smaller:

There are some differences to the original M9302:

•  the voltage dividers are not 178 / 383 ohm, but 180 / 390 ... the ratio error is 1%.
•  the source voltage for the terminators can be separated from +5V.
  By varying the terminator voltage, "Margin Testing" on the bus can be performed, as described by DEC.
•  the M9302 terminator has "SACK turnaround logic."
  This function answers any BUS GRANT with a proper SACK, if a GRANT is ignored by all device cards.
  Here it can be disabled by a jumper, converting UniProbe back into an older M930 terminator.

 

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Written by: Administrator

Parent Category: Tools

Category: UniProbe - an UNIBUS signal adapter

There are 2 different "UNIBUS" connectors on PDP-11 backplanes.

The "Standard UNIBUS" slot typical sits at the edge of backplanes, and is used to connect backplanes via UNIBUS BC11 white flat cable, or hold an terminator.

The "Modified UNIBUS" ("ModUB") often occupies Slot A and B of the hex socket which have an SPC in slots C to F.
It is optimized to hold memory cards and differs from the Standard UNIBUS:

• There are additional voltages for memory boards exposed.
  We have -5V and +20V for core, and Battery Backup voltages of -15V, +15V and +5V there.
• There is support for a separate parity controller (M7850). We have extra parity lines, and a internal SSYN signal, all that is not used in UniProbe.
•  the Bus GRANT lines BG4,5,6,7 and NPG, which are daisy chained from socket to socket, are missing.
  This has some advantage, as a card can plug into a ModUB socket without need to open or close GRANT jumpers.
  Just plug in "on-the-fly".
• the "SACK turnaround" logic of M9302 is not used. Good if you don't have these 8881 and 8837 DEC driver chips.
• as regular terminators remain plugged in, UniProbe on "Modified" sockets are not allowed to have own terminator packs.
  This makes UniProbe "neutral" to the bus, you can plug in and out without consequences.

Putting a standard UNIBUS card into a "ModUB" socket may cause major damage, as the >15V voltages are routed to signal wires then.
See the BIG warning label on the M9302 card!

 

Signal differences between Standard and Modified UNIBUS are (from the 11/34 system manual):

UniProbe can be build for either Standard or (exclusive or!) Modified UNIBUS sockets.
If build for ModUB:

• set the solder jumpers to 2-3 position
• do not populate the M9302 "SACK turnaraound logic" U1,U2,U3
• do not populate the BG4,5,6,7 and NPG LEDs
• replace the 180/390 ohm terminator resistors by high ohm 100k/100k.
  This allows for diagnostic of open signal wires: LEDs light with half intensity then.
• use a two-row male connector for voltage measuring, the additional supply voltages can be checked at the upper front connector row.
• clear the "Standard UNIBUS" text in the warning label!

SPC or UNIBUS?

Building UniProbe for the 4-row SPC socket would also have been a good idea.

• SPC also carries many voltages AND the bus grant signals simultaneously.
• SPC carries also the clock signal LTC and on some CPU backplanes (11/34) CPU HALT.
• it is 4 slots width, so more space available. A design without SMD chips would be possible.
• is also very popular and available on most (all?) PDP-11 systems somewhere.

However there are situtations where the SPC slot is not available.

• in tape drives like TU56 "DECtape" or TU10, where the controller is built into the tape drive rack and UNIBUS is routed through the separate rack.
• in rack boxes which contain ONLY special controller backplanes (like RK11 for RK05 drives, or RK611 for RK06 disks).
  These backplanes always have Standard UNIBUS slots, but never SPC.
• finally, DEC used the flat white UNIBUS cable BC11 and the M930 terminator also for non-UNIBUS busses. For example to daisy chain TM10 slave tape drives or RK05 disk drives.
  Despite we have completely different signals there, UniProbe's LEDs and logic analyzer connnectors may be useful in these setups too.

Prefering the UNIBUS slot over SPC is in fact a decision for flexibility and against comfort.

 

Details

Written by: Administrator

Parent Category: Tools

Category: UniProbe - an UNIBUS signal adapter

All 56 UNIBUS signals are shown by diagnostic LEDs on card front. Also supply powers are routed out for easy testing.

The LEDs are of 1.8mm type, these fit in the 100mil grid. They should be mounted looking vertical out of the case, this needs a 3D printed mount:

 

The 3D model for the mount are attachements on this page.

 

When viewing onto the card front from outside the PDP-11 card cage, we see these indicators:

1. Far left power connector:

2. Left half of LEDs:

3. Right half of LEDs:

These LEDs ares not just to have a light show. Dead bus driver may cause constant "active" levels, these are visible immediately.

Also an open "GRANT" chain shows up immediately by "active" BG* signals.

The LED drivers are analogous op amps, the LEDs show the voltage level ... which may be of some use. Input impedance is very high, so an open signal input may cause irregular flicker.

Most LEDs are lit on "LOW" voltage on the bus, as this is defined as "active" or "asserted". Only BG4,5,6,7,NPG light on "High".