Time scales of a PDP-11/34
Take a journey into a running PDP-11/34!
A logic analyzer is connected to various CPU signals, and the '34 is powered on.
Then we zoom into different time scales between 100 millisconds and 10 nanosconds and watch what the CPU is doing.
Of course this article is influenced by the famous video "Powers of Ten", which was created only a few years after the PDP-11/34. (Must link to the xkcd version here!
Time scales of a PDP-11/34 - 200 ns
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If we zoom the logic analyzer picture to 200 nanoseconds, we're at the level of electrical chip signals.
See your PDP-11/34 adding two numbers!
We focus on the "data path" board M8265. Still remember the main signal loop?
Data is processes in a 16-bit width signal. But all the standard chips for ALU, multiplexers, register memory and bus drivers are only available in 4-bith width, so the whole data path logic consists of four almost identical 4-bit slices. Here we will only examine the slice for bits 3 to 0.
Now the analyzer probes attached to the local CPU register memory chip (Scratch Pad Memory, SPM) come into play.
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The 85S68 is a fast 16x4 bit memory with seperate data inputs and data outputs. Additional there's an extra 4-bit latch for the outputs, so the outputs can hold the result of the last "read" while new data is written into another address in parallel.
Four of these chip implement the CPU registers R0..R15. For a the programmer, a PDP-11 has only eight registers R0..R5, R6=SP and R7=PC. The extra registers R8..R15 are used to
- save intermediary result for long micro programs like MULtiply and DIVide,
- for address calculation in complex addressing modes,
- and as alternate SP and PC registers for faster switching between kernel and user mode.
Signals
SPM.A0:3 - 4 address lines for 16 CPU registers R0..R15
SPM.D0:3 - 4 bit data inputs
SPM.M0:3 - 4 bit latched data outputs
SPM.CLK - data is written or read on Lowto High transistion
SPM.WE - write enable: Low level means data is written into chip on clock
SP.OS - "output store". While Low, data on SPM.M are the result of the last addressed location. If High, SPM.M shows data directly addressed by SPM.A.
PROCCLK - High to Low transition starts the next micro step.
What you see
We're looking at the first instruction the PDP-11/34 is executing after power-on. We're in microstep 0x00D = 015. The step before was 016, were data has been fetched from UNIBUS into the instruction register IR. Now in step 015 the PC in R7 is incremented by two, from 165020 to 165022.
We're only looking at the signals on the SPM now.
Only the lower 4 bits 3:0 are of the internal data path are shown (still too few LA probes!). So instead seeing R7 changing from 165020 to 165022, we see a transition from 0 to 2.
Incrementing R7 is performed in those steps, all approx. 30 nanoseconds apart:
| Marker | Signals | Info |
| C | PROCCLK Low, MPC = 0x00D = 015 |
Micro step 015 starts: PC := PC + 2 |
| D |
SPM.A := 7 |
Register address of PC = "7" is generated on the control board and arrives at SPM address inputs Current content of R7 is 165020, so SPM.D0:3 is 0 Data output shows content of R7 = 0 after delay, but now change is visible. |
| E | SPM.A changing from 7 to 7 |
The generic form for "PC := PC +2" is |
| E | SPM.D changing |
Other multiplexers and latches switch, SPM.D inputs flicker. |
| F | SPM.D := 2 | ALU has made the addition, the result "2" has run through the multiplexers and arrives at SPM data inputs again. |
| G | SPM.CLK Low->High, SPM.WE Low |
The new value "2" for R7 is saved in the SPM register. |
| H | PROCCLK High->Low | Next micro step starts (MPC = 0x020 = 040) |
A total signal round trip lasts from marker "D" to marker "G", this are approximately 100 nanoseconds! The PDP-11/34 CPU is build with 74Sxx chips. A simple 74Sxx gate should have just 3 nanoseconds delay, but SPM access and ALU operation take most of the time.
Control board loop
Beside data processing on "data path" board, there's also processing of the MPC on the "control" board. In parallel to the "PC := PC + 2" operation, the instruction register IR is decoded to get the start MPC for the instruction execution micro program.
In the screen shot, building the next MPC after 0x00D = 015 starts at mark "C" (where the next MPC is fetched from the micro store ROM at address 015), and is terminated at mark "G". Time is about 75 nanoseconds. This period is needed, because in micro step 015 the instruction register IR is decoded by a bunch of auxillary ROMs. Result of decoding are signals for ALU, multiplexers, source and destination register addresses, and a bit pattern which is added to the current MPC. This way the next MPC is calculated to 0x20 = 040.
Time scales of a PDP-11/34 - 1 µs
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If we enlarge the view to 1 microsecond, the operation of the micro machine comes into view.
Signals
MSYN. SSYN: UNIBUS handshake signals between CPU and ROM
PROCCLK: clock of micro machine
MPC: 9 bit micro program counter, which addresses the micro instructions.
What you see
The screen shot shows the micro steps following the fetch of the first instruction after BOOT. Marker "D" is at the same position as in the previous zoom level.
You can distinguish four pulses of clock signal PROCCLK. This is the basic CPU clock for the micro program counter. Modern micro processors have a clock corresponding to the instruction cycle, but the PDP-11 has a clock signal driving the micro machine. The pulses are some 200 nanosconds apart and 30ns width.
The micro program counter changes a lot, but on the falling edge of PROC CLK it is always stable. At this point the next micro instruction is fetched and executed, after that the MPC changes again as result of address re-calculation.
The micro steps in the screen shot are these:
| Marker | MPC (hex) |
MPC (octal) |
DEC original |
Info |
| D | 0x00E | 016 |
Fetch next instr,
|
SSYN Low->High |
| C | 0x00D | 015 | Increment PC, Micro branch on instruction |
R7 is increment by 2 |
| E | 0x020 | 040 | SOP |
Data "5003" is decoded. The MPC is cleared and overlaid with data from the instruction decoder ROMs. The "CLR" instruction needs only one micro step. |
| F | 0x000 | 000 | Service Intr/Traps, store vector |
After every instruction, the loop returns to MPC 000. Here status bits are scanned for errors or interrupts. |
| G | 0x00E | 016 | Fetch next instr, load into IR |
Again the next instruction is fetched from UNIBUS, MSYN will go low as soon SSYN goes low and the UNIBUS is released (the ROM still has SSYN High!) |
See the start of the micro code flow charts in the PDP-11/34 field maintenance print set:
Some remarks
Normally the cycles begins at MPC = 000 (trap service). But the instruction fetch at MPC=016 lasts very long, and PROC CLOCK is stopped until SSYN goes High again. Therefore we show here the steps between two fetches, from MPC=016 until MPC is 016 again.
At MPC = 000, the existence of traps, interrupts or error signals is checked. On any condition a branch to special micro code is executed. (Perhaps you learned the distinction between fast "Interrupt driven I/O" and slow "polled I/O" ? Well, here you see that on the micro code level, interrupts are merely polled by the micro code loop.)
At MPC =015, the program counter in R7 is incremented by 2. We will dive into this on the next page!
Between the PROCCLK pulses, there's a lot of changing on the MPC lines. Normally the next MPC is given by the current micro word (each micro instruction contains an implicit "GOTO"). But as signals loop through the data path circuits, MPC lines may be changed to execute "Branch On Micro Tests", so MPC has a lot of noise on it.
Time scales of a PDP-11/34 - 50 µs
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50 microseconds - CPU startup phases
Because the Power-On sequence is quite slow we have to zoom in from 200 milliseconds to 50 microsconds to see a new level of detail.
Signals
Relevant here signals are:
PROCINIT - High means: CPU is held in reset.
PROCCLK - internal CPU clock, drives the micro machine
MPC - the micro program counter
MSYN, SSYN, Addr, BUScycle, DATA - UNIBUS signals
What you see
You can recognize three different phases:
Phase 1: Reset
While PROC INIT is High, the CPU is held in reset. There's no signal activity.
Phase 2: micro coded selftest
As PROC INIT goes inactive, the CPU clock PROC CLK begins to oscillate (marker "A").
For the first 10 microseconds, there's a activity on MPC without UNIBUS signals.
Question: What is the CPU doing if it's not fetching program code from its BOOT ROM?
Answer: You see an internal selfest running, which is totally implemented in microcode. Here the basic function of the CPU is checked by clearing and incrementing the Program counter. A good part of the data path module is checked this way. See part of the self test micro program flow chart:
In case of an error, the micro code would clear the instruction register IR. Since opcode 000000 is a HALT, the CPU would stop then.
Phase 3: Start code execution
After selftest, the CPU begins fetching code and executing it, UNIBUS activity is visible (marker "E").
You see the characteristic patterns of UNIBUS signals: Overlapping MSYN and SSYN signals, as well as changing addresses and data lines.
Signal MSYN here means: "CPU has put a valid address onto the UNIBUS", while SSYN is the repsonse from the BOOT ROM: "Data read and valid".
At first an address is fetched from fixed vector 24, then execution starts from this address. If a Boot ROM card M9312 is inserted, the start address is manipulated point to one of the ROMs on M9312.
Time scales of a PDP-11/34 - 200 ms
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200 milliseconds - the CPU starts up after Power-ON
In a time window of 0.2 seconds, you see how the CPU begins to run after the reset logic has processed the signals of the power supply:
Signals
Relevant signals here are:
ACLO: a High level means "AC line power is unreliable".
DCLO: a High means: The main +5V logic supply voltage is unreliable.
PROCINIT: this signal is inverted, a High means: CPU is held in Reset, CPU clock is stopped.
What you see
- After power is switched ON, all signals are undefined at first. The LA shows them as Low levels.
- At the "T" marker, DCLO and ACLO from the power supply get valid and indicate a "Power failure".
The micro program counter MPC is initialized to 001, which is the start of the power-up micro program.
All other signals show constant nonsense data. - After Power has stabilized, DCLO goes Low ("A" marker").
- 120 milliseconds later, the PROC INIT signals goes inactive (marker "B").
- The CPU begins to run. You see all other signals begin to oscillate so fast, that no signal traces can be distinguished at 200ms resolution.
Time scales of a PDP-11/34 - Introduction
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I always was fond of logic analyzers, and I also admire the design of those DEC PDP-11 CPUs. So I operate a PDP11/34.
A big box
And when my 50th birthday came, I made myself a long desired present: a semi-professional logic analyzer with 70 channels.
A smaller box
Hooking those two devices together (combined with my appetite to write mediocre technical articles) resulted in this journey into a starting PDP-11/34.
Setup
See here the 11/34 under test in my lab:
Both CPU boards sit on extenders. The M8265 "data path" board is the upper one and the M8266 "control" board is the lower one. A total of three extenders is used, making the set-up quite sensitive to failures.
Logic analyzer probes are connected to UNIBUS signals as well as to the internal micro program counter and the chips which make up the CPU registers. See here for the UNIBUS signal adapter.
The LA screen shot
The logic analyzer is a ZEROPLUS device with USB interface. Its control software runs on the PC desktop, so making screen shots is easy:
There are many more of those logic analyzer screen shots to follow, so some words of explanation:
Time axis is horicontal, time running from left to right. Time legend is on top. The signal colors have no meaning. Either single wires or "buses" are shown. If severals electrical lines are combined to a bus signal, the resulting bus signal value is printed into the trace (as in "0x0B62". All values are hexadecimal, which is a real mess, since all PDP-11 docs use octal notation. Every screen shot shows the same signals, but on each zoom level only a subset of these signals is of interest.
And the meaning of all these signals is explained later.
What is shown?
In order to interpret what the logic analyzer shows here, a rough understanding of the 11/34 CPU is needed. I marked the displayed signals red in the schematics below.
The '34 CPU logic (as many mid-range PDP-11 CPU) is distributed onto two boards.
Data
The "DATA PATH" board, which does the actual calculation work. It contains CPU registers, the ALU (arithmetical-logical unit), most of the interface to the UNIBUS for data exchange, and various multi-way switches, so-called "multiplexers".
Every line in the diagram stands for a 16-wire data bus. The internal data flows in a big loop from UNIBUS to the CPU registers (labeled "Scratch Pad Memory", or "SPM") through ALU and several multiplexer (AMUX and SSMUX) back to the UNIBUS interface. The function of registers, multiplexers and ALU is controlled by signals from the "control" board.
Control
The other board is the CONTROL board: it contains the "micro machine", build mainly from instruction decoder, "micro store", micro program counter (MPC) and branch logic (BUT).
See here a schematic for the PDP-11/05 micro machine, the 11/34 is similar.
First the current instruction is fetched into the instruction register "IR". Then the instruction decoder calculates the starting micro program counter to be processed.
The "control store" contains list of signal patterns, which control the data path. Each pattern (called micro word) is addressed by the micro program counter "MPC", which after each step is moved a new value, depending on the executed micro word and lot of logical conditions ("MICRO BRANCH CONTROL").
One PDP-11 instruction is executed by a short (or longer) seqence of micro words, so called "micro programs".