UniProbe - Logic analyzer interface

Parent Category: Tools Category: UniProbe - an UNIBUS signal adapter Written by Administrator

All 56 Unibus signals are routed to plugs for logic analyzer ("LA") probes.

uniprobe3d laconnectors

There's no way to repair a PDP-11 without logic analyzer. Today you have typically two choices:

So when working with logic analyzers on PDP-11s, the main challenge is to deal with limited probe count. In theory UNIBUS traffic needs 56 signals wires on its own, before any tracing in the circuitry can start. But you can get a feeling of bus traffic by just watching data, a few lower address lines and some protocol signals.

To help a bit, UniProbe allows to connects flexible only a subset of UniBus cables to the LA, leaving other LA signals for circuit diagnostics.



Probe connectors

Seven 8-channel plugs for LA cables are provided, labeled "A-Lo", "A-Hi", "B-Lo", etc. until "D-Lo".

UniProbe supports the "Zeroplus" probe standard: A probe cable carries 8 signals on a standard flatcable. Typical 2x8 pinheaders are crimped to the cable.

Output on the LA is (view onto the LA case):

Male signal pins  Usage
 7  6  5  4  3  2  1  0  upper row: Signals
 G  G  G  G  G  G  G  G  lower row: Ground

UniProbe contains the mating female sockets. View onto the connector front:

Female signal sockets  Usage
 0  1  2  3  4  5  6  7  upper row: Signals
 G  G  G  G  G  G  G  G  lower row: Ground


Mapping channels to UNIBUS signals

There is support for 3 signal mapping styles:

"Hard wired mapping": UNIBUS DATA <15:00> and ADDR<07:00> are always connected to probes "A-Lo", "A-Hi" and "B-Lo".
I can imagination no situation were you don't need to see these.

"Fixed position jumper mapping": To display the regular UNIBUS data cycle, signals ADDR<17:08>,C0,C1,MSYN,SSYN are needed. As I have a 70 channel LA and want to see these always, jumper brigdes are provided to save on plug wires.

"Patch panel mapping":For all other signals a patchpanel is provided. Every remaining UNIBUS signal can be routed freely to any LA probe plug. This allows for greatest flexibility and ensures no LA channels are wasted.

uniprobe wires


Additionally, a special "IOPAGE" signal is added, which decodes addresses in the 760000 range. Its just the OR of ADDR<17:13>, so five wires are replaced by a single wire for "IOPAGE". Only if ADDR<17:13> are all Low (= logic "1"), IOPAGE is also Low (= logic "1"). Together with A<07:00> this allows to follow peripheral accesses and program execution with just 9 address lines.

Organizing all these wires

From painful experience, UniProbe has functions to tame the LA cable tree.


Importance of inline-terminators

High frequency signals behave like water waves: they get reflected on cable ends, if the receivers impedance does not match cables wave resistance. Logic analyzer inputs have an impedance of > 100kOhm, but if the probes are lengthed with flat cable we get 100-150 ohm per meter extra. This additional impedance must be damped by resistors inserted into the wires. UniProbe has positions for these resistors.

This is indeed important, see example. Here the transition of address line ADDR00 from "inactive" to "asserted" (logic 0 to 1) is shown.

The "blue" signal is measured at the UNIBUS pin, "red" is at the logic analyzer inputs via 50cm flat cable. The scope had a bandwidth of 200MHz, scale division is 20ns.

Without inline terminators, you see:

The frequency of the oscillation is surprisingly low: 40ns peak-to-peak, about 25MHz. Apparently the cables form an inductivity-capacity (LC) resonator .

term 0ohm d0assert d0 7toggle

Here with 82 ohm terminators the reflections are damped, while preserving signal levels and timing:

term 68ohm d0assert d0 7toggle

The best resistors values depend from quite a few factors and must be optimized individually for each probe&logic analyzer combination.