QProbe - Logic Analyzer Interface

Parent Category: Tools Category: QProbe - a QBUS signal adapter Written by Administrator

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Synthetic CPLD-to-LA signals

"Address<15.00>" signals are generated by CPLD and normally contain the demultiplex address bits from BDAL 15..0

However, own CPLD logic may use these signals to generate special signals, for example to trigger a logic analyzer at certain compelx bus conditions.

Already implmeneted is a HALT catcher:

Wehen running diagnsotci programs on a PDP-11, you typically execute a HALT opcode on some error condition. You liek to trigger the anylyzer on that HALt event, but there is bnot bus line indicating a CPU (BHALT is input to the CPU only). Infact a QBUS-CPU never HALTs like a UNIBUS CPU, isntead the micrcoded ODT monitor starts and polls the console UART for input.

This is used to regcongize a HALT condition: A special CPLD mode sets the ADDRESS0 pin, if two consequitve accesses to the UART address range at 77560.. 777566 ar detedcted. Regular code which polls UART in a tight loop needs at least to fecth program opcode to access to UART, only micro coded ODT can access UART without generating other bus cycles.

Ther's on excpetion: If the CPU executes program from a memory cache, no program fetches are visible on QBUS and the CPLD logic gives false HALT.