Interpreting UNIBUS signals

This is the sequel to the "UNIBUS signal adapter" article.

I connected my little Intronix USB logic analyzer to the UNIBUS in my defective PDP-11/05. He has 32 signals lines and 500MHz resolution.

 

Some basics

The UNIBUS has an asynchronous protocol, I'm skipping most of it's features here.

Before each "data transfer" bus cycle an "piority arbitration" is performed.

Transmission is always between a "master" (mostly the processor) and a "slave" (a memory card or an I/O device).

For basic read/write, only these signals are used:

ADDRESS: there are 18 address lines,

DATA: there are 16 DATA lines

CONTROL: lines C1 and C0 identify the bus cycle type. There are:

C1	C0	Cycle	Info
0	0	DATI	read word
0	1	DATIP	read word, next instruction will write to same address (core memory had a destructive read. If the data is written back by the processor the restore cycle can be skipped).
1	0	DATO	write word
1	1	DATOB	write byte

MSYN: Master Sync

SSYN: Slave Sync

All lines mentioned here are low-active. This means, an "active" (or "asserted") state of a signal is electrically encoded as a 0 Volt level.

But here in the logic anayzer an active line is shown as "1".

UNIBUS read cycle

Here is a shot of a read cycle:

Address 0x006e is read, the result is 0x8401. The sequence is:

1. The master (the CPU) sets C1,C0 to DATI, and sets the ADDRESS lines. Then he asserts MSYN asserted (Cursor A).
2. All devices on the bus evaluate ADDRESS. The selected slave device (memory or I/O card) puts DATA onto the bus. Then it asserts SSYN.
3. The master reads DATA. Then he clears MSYN. (Cursor B).
4. The slaves notices the master is reads, removes DATA from the bus and cleares SSYN.

UNIBUS write cycle

Here is a write:

 Valu 0x8000 is written to address 0x00d4. The sequence is

1. The master (the CPU) sets C1,C0 to DATO and puts ADDRESS and DATA onto the bus. Then he asserts MSYN (Cursor A).
2. All slave devices (memory cards and I/O cards) decode ADDRESS. The selected slave reads in DATA and processes them. Then he asserts SSYN.
3. The master removes DATA from the bus and cleares MSYN (Cursor B).
4. The slave device notices bus cycle is over and clears SSYN.

 

After each transition of MSYN or SSYN delays of 75ns and 150 ns defined. This guarantees that line level progagate along the UNIBUS lines to all attached devices. A single UNIBUS may cross many racks, with long connection cables in between).