If we zoom the logic analyzer picture to 200 nanoseconds, we're at the level of electrical chip signals.
See your PDP-11/34 adding two numbers!
We focus on the "data path" board M8265. Still remember the main signal loop?
Data is processes in a 16-bit width signal. But all the standard chips for ALU, multiplexers, register memory and bus drivers are only available in 4-bith width, so the whole data path logic consists of four almost identical 4-bit slices. Here we will only examine the slice for bits 3 to 0.
Now the analyzer probes attached to the local CPU register memory chip (Scratch Pad Memory, SPM) come into play.
The 85S68 is a fast 16x4 bit memory with seperate data inputs and data outputs. Additional there's an extra 4-bit latch for the outputs, so the outputs can hold the result of the last "read" while new data is written into another address in parallel.
Four of these chip implement the CPU registers R0..R15. For a the programmer, a PDP-11 has only eight registers R0..R5, R6=SP and R7=PC. The extra registers R8..R15 are used to
- save intermediary result for long micro programs like MULtiply and DIVide,
- for address calculation in complex addressing modes,
- and as alternate SP and PC registers for faster switching between kernel and user mode.
SPM.A0:3 - 4 address lines for 16 CPU registers R0..R15
SPM.D0:3 - 4 bit data inputs
SPM.M0:3 - 4 bit latched data outputs
SPM.CLK - data is written or read on Lowto High transistion
SPM.WE - write enable: Low level means data is written into chip on clock
SP.OS - "output store". While Low, data on SPM.M are the result of the last addressed location. If High, SPM.M shows data directly addressed by SPM.A.
PROCCLK - High to Low transition starts the next micro step.
What you see
We're looking at the first instruction the PDP-11/34 is executing after power-on. We're in microstep 0x00D = 015. The step before was 016, were data has been fetched from UNIBUS into the instruction register IR. Now in step 015 the PC in R7 is incremented by two, from 165020 to 165022.
We're only looking at the signals on the SPM now.
Only the lower 4 bits 3:0 are of the internal data path are shown (still too few LA probes!). So instead seeing R7 changing from 165020 to 165022, we see a transition from 0 to 2.
Incrementing R7 is performed in those steps, all approx. 30 nanoseconds apart:
MPC = 0x00D = 015
|Micro step 015 starts: PC := PC + 2|
SPM.A := 7
|Register address of PC = "7" is generated on the control board and arrives at SPM address inputs
Current content of R7 is 165020, so SPM.D0:3 is 0
Data output shows content of R7 = 0 after delay, but now change is visible.
from 7 to 7
The generic form for "PC := PC +2" is
Other multiplexers and latches switch, SPM.D inputs flicker.
|F||SPM.D := 2||ALU has made the addition, the result "2" has run through the multiplexers and arrives at SPM data inputs again.|
|The new value "2" for R7 is saved in the SPM register.|
|H||PROCCLK High->Low||Next micro step starts (MPC = 0x020 = 040)|
A total signal round trip lasts from marker "D" to marker "G", this are approximately 100 nanoseconds! The PDP-11/34 CPU is build with 74Sxx chips. A simple 74Sxx gate should have just 3 nanoseconds delay, but SPM access and ALU operation take most of the time.
Control board loop
Beside data processing on "data path" board, there's also processing of the MPC on the "control" board. In parallel to the "PC := PC + 2" operation, the instruction register IR is decoded to get the start MPC for the instruction execution micro program.
In the screen shot, building the next MPC after 0x00D = 015 starts at mark "C" (where the next MPC is fetched from the micro store ROM at address 015), and is terminated at mark "G". Time is about 75 nanoseconds. This period is needed, because in micro step 015 the instruction register IR is decoded by a bunch of auxillary ROMs. Result of decoding are signals for ALU, multiplexers, source and destination register addresses, and a bit pattern which is added to the current MPC. This way the next MPC is calculated to 0x20 = 040.