Time scales of a PDP-11/34 - 50 µs

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50 microseconds - CPU startup phases

Because the Power-On sequence is quite slow we have to zoom in from 200 milliseconds to 50 microsconds to see a new level of detail.

la shot 50us



Relevant here signals are:

PROCINIT - High means: CPU is held in reset.

PROCCLK - internal CPU clock, drives the micro machine

MPC - the micro program counter

MSYN, SSYN, Addr, BUScycle, DATA - UNIBUS signals


What you see

You can recognize three different phases:

Phase 1: Reset

While PROC INIT is High, the CPU is held in reset. There's no signal activity.

Phase 2: micro coded selftest

As PROC INIT goes inactive, the CPU clock PROC CLK begins to oscillate (marker "A").

For the first 10 microseconds, there's a activity on MPC without UNIBUS signals.

Question: What is the CPU doing if it's not fetching program code from its BOOT ROM?

Answer: You see an internal selfest running, which is totally implemented in microcode. Here the basic function of the CPU is checked by clearing and incrementing the Program counter. A good part of the data path module is checked this way. See part of the self test micro program flow chart:

microcode flow selftest detail

In case of an error, the micro code would clear the instruction register IR. Since opcode 000000 is a HALT, the CPU would stop then.


Phase 3: Start code execution

After selftest, the CPU begins fetching code and executing it, UNIBUS activity is visible (marker "E").

You see the characteristic patterns of UNIBUS signals: Overlapping MSYN and SSYN signals, as well as changing addresses and data lines.

Signal MSYN here means: "CPU has put a valid address onto the UNIBUS", while SSYN is the repsonse from the BOOT ROM: "Data read and valid".

At first an address is fetched from fixed vector 24, then execution starts from this address. If a Boot ROM card M9312 is inserted, the start address is manipulated point to one of the ROMs on M9312.